Implementing known scrambling relationship among multiple serial links

ABSTRACT

A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field,and more particularly, relates to a method and circuit for implementingknown scrambling relationship among multiple serial links, and a designstructure on which the subject circuit resides.

DESCRIPTION OF THE RELATED ART

High speed serial (HSS) links are used for communications in variousknown computer chips and computer systems. A given computer chip mayinclude multiple instances of a specific HSS link using the sameinterface protocol. Many HSS interfaces utilize Linear Feedback ShiftRegisters (LFSRs) to scramble the data that is transmitted. Thisscrambling provides many advantages; however, synchronization isrequired to accurately de-scramble the received data bit stream.

Each serial link protocol generally provides its own unique mechanismfor achieving such synchronization. In conventional arrangements,typically both the transmit LFSR and the receive LFSR are initialized toa predefined starting value based upon when a given stage of an overallLink Initialization Procedure (LIP) takes place.

In a computer chip having multiple HSS link interfaces, it would bepreferable to avoid the situation of some conventional arrangementswhere multiple transmit LFSRs are initialized to their starting value,and then multiple HSS interfaces are scrambling their IDLE patterns inthe exact same way at the exact same time. In prior art arrangements,both the transmit LFSR and the receive LFSR can be initialized to acommon predefined value, such as all ones. When all links aretransmitting using the same LFSR value, then the electromagneticinterference (EMI) radiation of each link may add together producingstronger interference.

A need exists for an effective method and circuit to guarantee that foreach HSS link interface, the scrambling LFSR has a different valueduring normal operation than the scrambling LFSR of each of the multipleother serial links. Such method and circuit are needed so that theirIDLE patterns will be different from one another and adding of the EMIradiation of each link is substantially avoided.

SUMMARY OF THE INVENTION

Principal aspects of the present invention are to provide a method andcircuits for implementing known scrambling relationship among multipleserial links, and a design structure on which the subject circuitresides. Other important aspects of the present invention are to providesuch method, circuitry, and design structure substantially withoutnegative effect and that overcome many of the disadvantages of prior artarrangements.

In brief, a method and circuits for implementing known scramblingrelationship among multiple serial links, and a design structure onwhich the subject circuit resides are provided. A transmit LinearFeedback Shift Register (LFSR) is provided with each of the multipleserial links for scrambling transmitted data. A receive Linear FeedbackShift Register (LFSR) is provided with each of the multiple serial linksfor descrambling received data. Each of the transmit LFSRs isinitialized to a unique value. Each transmit LFSR conveys a currentunique value to a receive LFSR, for synchronizing the transmit LFSR andreceive LFSR to begin scrambling and descrambling data.

In accordance with features of the invention, a multiple-path local rackinterconnect system includes a plurality of interconnect chips, and aplurality of serial links connected between each of the plurality ofinterconnect chips. Each of the interconnect chips includes a pluralityof link interfaces for implementing known scrambling relationship amongmultiple serial links of the plurality of serial links. Each linkinterface is connected to a respective one of the multiple serial links.Each link interface includes a transmit Linear Feedback Shift Register(LFSR) for scrambling transmitted data; and a receive Linear FeedbackShift Register (LFSR) for descrambling transmitted data. Each transmitLFSR is initialized with a unique value; and conveys a current uniquevalue to a receive LFSR for synchronizing the transmit LFSR and receiveLFSR to begin scrambling and descrambling data.

In accordance with features of the invention, the unique value is basedupon an interface number of each said transmit LFSR. Each of thetransmit LFSRs is initialized to a unique value during power-on, andcontinues running for the life of the power-on. Each transmit LFSRconveys a current unique value to a receive LFSR for synchronizing thetransmit LFSR and receive LFSR during a link training sequence.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention together with the above and other objects andadvantages may best be understood from the following detaileddescription of the preferred embodiments of the invention illustrated inthe drawings, wherein:

FIGS. 1A, 1B, 1C, 1D, and 1E are respective schematic and block diagramsillustrating an exemplary a local rack interconnect system forimplementing known scrambling relationship among multiple serial linksin accordance with the preferred embodiment;

FIG. 2 illustrates a single high speed serial link circuit includingLinear Feedback Shift Registers (LFSRs) of the interconnect chip ofFIGS. 1A-1E in accordance with the preferred embodiment;

FIG. 3 illustrates multiple instances of the high speed serial linkcircuit of FIG. 2 for implementing known scrambling relationship amongmultiple serial links in accordance with the preferred embodiment;

FIG. 4 is a flow chart illustrating exemplary operations performed bythe high speed serial link circuits of FIGS. 2 and 3 for implementingknown scrambling relationship among multiple serial links in accordancewith the preferred embodiment; and

FIG. 5 is a flow diagram of a design process used in semiconductordesign, manufacturing, and/or test.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of embodiments of the invention,reference is made to the accompanying drawings, which illustrate exampleembodiments by which the invention may be practiced. It is to beunderstood that other embodiments may be utilized and structural changesmay be made without departing from the scope of the invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

In accordance with features of the invention, circuits and methods areprovided for implementing known scrambling relationship among multipleserial links. The methods and circuits of the invention guarantee thatthe scrambling Linear Feedback Shift Register (LFSR) of each high speedserial (HSS) link interface have a different value during normaloperation; therefore their IDLE patterns will be different from oneanother so that the electromagnetic interference (EMI) radiation of eachlink will not add. In conventional arrangements, typically EMI radiationof each link adds together producing stronger interference, for example,where LFSRs of multiple HSS link interfaces are initialized with thesame value.

Having reference now to the drawings, in FIG. 1A, there is shown anexample multiple-path local rack interconnect system generallydesignated by the reference character 100 used for implementing knownscrambling relationship among multiple serial links in accordance withthe preferred embodiment. The multiple-path local rack interconnectsystem 100 supports computer system communications between multipleservers, and enables an Input/Output (IO) adapter to be shared acrossmultiple servers. The multiple-path local rack interconnect system 100supports network, storage, clustering and Peripheral ComponentInterconnect Express (PCIe) data traffic.

The multiple-path local rack interconnect system 100 includes aplurality of interconnect chips 102 in accordance with the preferredembodiment arranged in groups or super nodes 104. Each super node 104includes a predefined number of interconnect chips 102, such as 16interconnect chips, arranged as a chassis pair including a first and asecond chassis group 105, each including 8 interconnect chips 102. Themultiple-path local rack interconnect system 100 includes, for example,a predefined maximum number of nine super nodes 104. As shown, a pair ofsuper nodes 104 are provided within four racks or racks 0-3, and a ninthsuper node 104 is provided within the fourth rack or rack 4.

In FIG. 1A, the multiple-path local rack interconnect system 100 isshown in simplified form sufficient for understanding the invention,with one of a plurality of local links (L-links) 106 shown between apair of the interconnect chips 102 within one super node 104. Themultiple-path local rack interconnect system 100 includes a plurality ofL-links 106 connecting together all of the interconnect chips 102 ofeach super node 104. A plurality of distance links (D-links) 108, or asshown eight D-links 108 connect together the example nine super nodes104 together in the same position in each of the other chassis pairs.Each of the L-links 106 and D-links 108 comprises a bi-directional (×2)high-speed serial (HSS) link.

Referring also to FIG. 1E, each of the interconnect chips 102 of FIG. 1Aincludes, for example, 18 L-links 106, labeled 18 ×2 10 GT/S PERDIRECTION and 8 D-links 108, labeled 8 ×2 10 GT/S PER DIRECTION.

Referring also to FIGS. 1B and 1C, multiple interconnect chips 102defining a super node 104 are shown connected together in FIG. 1B. Afirst or top of stack interconnect chip 102, labeled 1,1,1 is showntwice in FIG. 1B, once off to the side and once on the top of the stack.Connections are shown to the illustrated interconnect chip 102, labeled1,1,1 positioned on the side of the super node 104 including a pluralityof L-links 106 and a connection to a device 110, such as a centralprocessor unit (CPU)/memory 110. A plurality of D links 108 or eightD-links 108 as shown in FIG. 1A, (not shown in FIG. 1B) are connected tothe interconnect chips 102, such as interconnect chip 102, labeled 1,1,1in FIG. 1B.

As shown in FIG. 1B, each of a plurality of input/output (I/O) blocks112, is connected to respective interconnect chips 102, and respectiveones of the I/O 112 are connected together. A source interconnect chip102, such as interconnect chip 102, labeled 1,1,1 transmits or spraysall data traffic across all L-links 106. A local 110 112 may also use aparticular L-link 106 of destination I/O 112. For a destination inside asuper node 104, or chassis pair of first and second chassis group 105, asource interconnect chip or an intermediate interconnect chip 102forwards packets directly to a destination interconnect chip 102 over anL-link 106. For a destination outside a super node 104, a sourceinterconnect chip or an intermediate interconnect chip 102 forwardspackets to an interconnect chip 102 in the same position on thedestination super node 104 over a D-link 108. The interconnect chip 102in the same position on the destination super node 104 forwards packetsdirectly to a destination interconnect chip 102 over an L-link 106.

In the multiple-path local rack interconnect system 100, the possiblerouting paths with the source and destination interconnect chips 102within the same super node 104 include a single L-link 106; or a pair ofL-links 106. The possible routing paths with the source and destinationinterconnect chips 102 within different super nodes 104 include a singleD-link 108 (D); or a single D-link 108, and a single L-link 106 (D-L);or a single L-link 106, and single D-link 108 (L-D); or a single L-link106, a single D-link 108, and a single L-link 106 (L-D-L). With anunpopulated interconnect chip 102 or a failing path, the L-link 106 isremoved from a spray list at the source interconnect 102.

As shown in FIGS. 1B and 1C, a direct path is provided from the centralprocessor unit (CPU)/memory 110 to the interconnect chips 102, such aschip 102, labeled 1,1,1 in FIG. 1B, and from any other CPU/memoryconnected to another respective interconnect chip 102 within the supernode 104.

Referring now to FIG. 1C, a chassis view generally designated by thereference character 118 is shown with a first of a pair of interconnectchips 102 connected a central processor unit (CPU)/memory 110 and theother interconnect chip 102 connected to input/output (I/O) 112connected by local rack fabric L-links 106, and D-links 108. Exampleconnections shown between each of an illustrated pair of servers withinthe CPU/memory 110 and the first interconnect chip 102 include aPeripheral Component Interconnect Express (PCIe) G3 ×8, and a pair of100 GbE or 2-40 GbE to a respective Network Interface Card (NIC).Example connections of the other interconnect chip 102 include up to7-40/10 GbE Uplinks, and example connections shown to the I/O 112include a pair of PCIe G3 ×16 to an external MRIOV switch chip, withfour ×16 to PCI-E I/O Slots with two Ethernet slots indicated 10 GbE,and two storage slots indicated as SAS (serial attached SCSI) and FC(fibre channel), a PCIe ×4 to a IOMC and 10 GbE to CNIC (FCF).

Referring now to FIGS. 1D and 1E, there are shown block diagramrepresentations illustrating an example interconnect chip 102. Theinterconnect chip 102 includes an interface switch 120 connecting aplurality of transport layers (TL) 122, such as 7 TLs, and interfacelinks (iLink) layer 124 or 26 iLinks. An interface physical layerprotocol, or iPhy 126 is coupled between the interface links layer iLink124 and high speed serial (HSS) interface 128, such as 7 HSS 128. Asshown in FIG. 1E, the 7 HSS 128 are respectively connected to theillustrated 18 L-links 106, and 8 D-links 108. In the exampleimplementation of interconnect chip 102, 26 connections including theillustrated 18 L-links 106, and 8 D-links 108 to the 7 HSS 128 are used,while the 7 HSS 128 would support 28 connections.

The TLs 122 provide reliable transport of packets, including recoveringfrom broken chips 102 and broken links 106, 108 in the path betweensource and destination. For example, the interface switch 120 connectsthe 7 TLs 122 and the 26 iLinks 124 in a crossbar switch, providingreceive buffering for iLink packets and minimal buffering for the localrack interconnect packets from the TLO 122. The packets from the TL 122are sprayed onto multiple links by interface switch 120 to achievehigher bandwidth. The iLink layer protocol 124 handles link level flowcontrol, error checking CRC generating and checking, and link levelretransmission in the event of CRC errors. The iPhy layer protocol 126handles training sequences, lane alignment, and scrambling anddescrambling. The HSS 128, for example, are 7 ×8 full duplex coresproviding the illustrated 26 ×2 lanes.

In FIG. 1E, a more detailed block diagram representation illustratingthe example interconnect chip 102 is shown. Each of the 7 transportlayers (TLs) 122 includes a transport layer out (TLO) partition andtransport layer in (TLI) partition. The TLO/TLI 122 respectivelyreceives and sends local rack interconnect packets from and to theillustrated Ethernet (Enet), and the Peripheral Component InterconnectExpress (PCI-E), PCI-E ×4, PCI-3 Gen3 Link respectively via networkadapter or fabric adapter, as illustrated by blocks labeled high speedserial (HSS), media access control/physical coding sub-layer (MAC/PCS),distributed virtual Ethernet bridge (DVEB); and the PCIE_G3 ×4, andPCIE_G3 2 ×8, PCIE_G3 2 ×8, a Peripheral Component Interconnect Express(PCIe) Physical Coding Sub-layer (PCS) Transaction Layer/Data/LinkProtocol (TLDLP) Upper Transaction Layer (UTL), PCIe Application Layer(PAL MR) TAGGING to and from the interconnect switch 120. A networkmanager (NMan) 130 coupled to interface switch 120 uses End-to-End (ETE)small control packets for network management and control functions inmultiple-path local rack interconnect system 100. The interconnect chip102 includes JTAG, Interrupt Handler (INT), and Register partition(REGS) functions.

In accordance with features of the invention, a protocol method andcircuit are provided for initializing the scrambling and descramblingLinear Feedback Shift Registers (LFSRs) in order to guarantee thatmultiple instances of the same interface on a given chip 102 are usingdifferent values at any given time. Each transmit LFSR is initialized toa unique value during power-on, starts running performing shiftingoperations, and continues to do so (non-stop) during the life of thatpower-on.

Referring now to FIG. 2, there is shown a single high speed serial linkcircuit generally designated by the reference character 200 forimplementing known scrambling relationship among multiple serial linksin accordance with the preferred embodiment. The single high speedserial link circuit 200 includes a respective HSS interface circuitdesignated by the reference character 202 included in each interconnectchip 102, A and B connected by L-link 106 or D-link 108. The HSSinterface circuit 202 includes a respective transmit or scramblingLinear Feedback Shift Register (LFSR) 204 coupled to the transmit sideof an L link 106 or a D link 108 of the high speed serial link circuit200. The HSS interface circuit 202 includes a respective descramblingLinear Feedback Shift Register (LFSR) 206 coupled to a receive side ofthe L link 106 or the D link 108 of the high speed serial link circuit200. The high speed serial (HSS) link circuit 200 is implemented in theHSS interface 128 of the interconnect chip 102 shown in FIGS. 1D and 1E.

FIG. 3 illustrates multiple instances generally designated by thereference character 300 of the high speed serial interface circuit 202of FIG. 2 for implementing known scrambling relationship among multipleserial links in accordance with the preferred embodiment. The respectivetransmit or scrambling Linear Feedback Shift Register (LFSR) 204 of eachof the multiple link interface circuits 202 receives a unique valueindicated by arrows labeled LINK VALUE 0-3. The unique value applied tothe respective transmit LFSR 204 is based, for example, upon aninterface number of each said transmit LFSR. Each of the transmit LFSRs204 is initialized to the unique value during power-on, then continuesrunning generally for the life of the power-on. Each of the transmitLFSRs 204 also would be initialized to the unique value during a rebootor reset of the interconnect chips 102 of the multiple-path local rackinterconnect system 100. Each transmit LFSR 204 conveys a current uniquevalue to a receive LFSR 206 for synchronizing the transmit LFSR andreceive LFSR during a link training sequence.

Referring now to FIG. 4, there are shown exemplary operations performedby the high speed serial link circuits 200, 300 of FIGS. 2 and 3 forimplementing known scrambling relationship among multiple serial linksin accordance with the preferred embodiment starting at power-on asindicated at a block 400. Each of the transmit LFSRs 204 is initializedto the unique value during power-on as indicated at a block 402, theunique value advantageously is based upon the interface number. Thetransmit LFSRs 204 are initialized or programmed using a selectedmechanism, for examples, by scanning in or loading a register value, orby wiring pins on the chip 102 to Vdd or ground. Each of the transmitLFSRs 204 starts running responsive to the initialized unique value, andcontinues running for the life of the power-on as indicated at a block404.

Next as indicated at a block 406 a link training sequence is performedto initialize or train each of the high speed serial links in themultiple-path local rack interconnect system 100. As shown at stepnumber n during the link training sequence, the transmit LFSR 204conveys a current unique value to a receive LFSR 206 for synchronizingthe transmit LFSR and receive LFSR. Then the descrambling LFSR 206 atthe receiver interconnect chip 102 is synchronized with the scramblingLFSR 204 at the transmitter interconnect chip 102 so that the bit streammay be accurately descrambled.

FIG. 5 shows a block diagram of an example design flow 500 that may beused for high speed serial link circuit and the interconnect chipdescribed herein. Design flow 500 may vary depending on the type of ICbeing designed. For example, a design flow 500 for building anapplication specific IC (ASIC) may differ from a design flow 500 fordesigning a standard component. Design structure 502 is preferably aninput to a design process 504 and may come from an IP provider, a coredeveloper, or other design company or may be generated by the operatorof the design flow, or from other sources. Design structure 502comprises circuits 102, 200, 300 in the form of schematics or HDL, ahardware-description language, for example, Verilog, VHDL, C, and thelike. Design structure 502 may be contained on one or more machinereadable medium. For example, design structure 502 may be a text file ora graphical representation of circuits 102, 200, 300. Design process 504preferably synthesizes, or translates, circuits 102, 200, 300 into anetlist 506, where netlist 506 is, for example, a list of wires,transistors, logic gates, control circuits, I/O, models, etc. thatdescribes the connections to other elements and circuits in anintegrated circuit design and recorded on at least one of machinereadable medium. This may be an iterative process in which netlist 506is resynthesized one or more times depending on design specificationsand parameters for the circuits.

Design process 504 may include using a variety of inputs; for example,inputs from library elements 508 which may house a set of commonly usedelements, circuits, and devices, including models, layouts, and symbolicrepresentations, for a given manufacturing technology, such as differenttechnology nodes, 32 nm, 45 nm, 90 nm, and the like, designspecifications 510, characterization data 512, verification data 514,design rules 516, and test data files 518, which may include testpatterns and other testing information. Design process 504 may furtherinclude, for example, standard circuit design processes such as timinganalysis, verification, design rule checking, place and routeoperations, and the like. One of ordinary skill in the art of integratedcircuit design can appreciate the extent of possible electronic designautomation tools and applications used in design process 504 withoutdeviating from the scope and spirit of the invention. The designstructure of the invention is not limited to any specific design flow.

Design process 504 preferably translates an embodiment of the inventionas shown in FIGS. 1A-1E, and 2-4 along with any additional integratedcircuit design or data (if applicable), into a second design structure520. Design structure 520 resides on a storage medium in a data formatused for the exchange of layout data of integrated circuits, forexample, information stored in a GDSII (GDS2), GL1, OASIS, or any othersuitable format for storing such design structures. Design structure 520may comprise information such as, for example, test data files, designcontent files, manufacturing data, layout parameters, wires, levels ofmetal, vias, shapes, data for routing through the manufacturing line,and any other data required by a semiconductor manufacturer to producean embodiment of the invention as shown in FIGS. 1A-1E, and 2-4. Designstructure 520 may then proceed to a stage 522 where, for example, designstructure 520 proceeds to tape-out, is released to manufacturing, isreleased to a mask house, is sent to another design house, is sent backto the customer, and the like.

While the present invention has been described with reference to thedetails of the embodiments of the invention shown in the drawing, thesedetails are not intended to limit the scope of the invention as claimedin the appended claims.

What is claimed is:
 1. A method for implementing known scramblingrelationship among multiple serial links comprising: providing atransmit Linear Feedback Shift Register (LFSR) with each of the multipleserial links for scrambling transmitted data; providing a receive LinearFeedback Shift Register (LFSR) with each of the multiple serial linksfor descrambling transmitted data; initializing each said transmit LFSRwith a respective unique value per link instance during power-on of themultiple serial links, each said transmit LFSR starts running responsiveto said respective initialized unique value per link instance, andcontinues running during life of the power-on; each said respectiveinitialized unique value per link instance being different from oneanother and substantially without adding of EMI radiation of each link;and performing a link training sequence to initialize each of themultiple serial links, said link training sequence including each saidtransmit LFSR, conveying said current unique value per link instance toa receive LFSR, for synchronizing said transmit LFSR and said receiveLFSR to begin scrambling data; each said respective current unique valueper link instance being different from one another for each saidtransmit LFSR.
 2. The method for implementing known scramblingrelationship among multiple serial links as recited in claim 1 whereininitializing each said transmit LFSR with a unique value includessetting said unique value based upon an interface number of each saidtransmit LFSR.
 3. A circuit for implementing known scramblingrelationship among multiple serial links comprising: a respective linkinterface coupled to each of the multiple serial links, each said linkinterface including a transmit Linear Feedback Shift Register (LFSR) forscrambling transmitted data; and a receive Linear Feedback ShiftRegister (LFSR) with each of the multiple serial links for descramblingtransmitted data; each said transmit LFSR being initialized with arespective unique value per link instance during power-on of themultiple serial links, each said transmit LFSR starts running responsiveto said respective initialized unique value per link instance, andcontinues running during life of the power-on; each said respectiveinitialized unique value per link instance being different from oneanother and substantially without adding of EMI radiation of each link;and each said transmit LFSR, performing a link training sequence toinitialize each of the multiple serial links, said link trainingsequence including conveying a current unique value per link instance toa receive LFSR, for synchronizing said transmit LFSR and said receiveLFSR to begin scrambling data; each said respective current unique valueper link instance being different from one another for each saidtransmit LFSR.
 4. The circuit for implementing known scramblingrelationship among multiple serial links as recited in claim 3 whereinsaid unique value is based upon an interface number of each saidtransmit LFSR.
 5. A multiple-path local rack interconnect systemcomprising: a plurality of interconnect chips; a plurality of seriallinks connected between each of said plurality of interconnect chips;each of said interconnect chips including a plurality of link interfacesfor implementing known scrambling relationship among multiple seriallinks of said plurality of serial links, each said link interface beingconnected to a respective one of the multiple serial links, each saidlink interface including a transmit Linear Feedback Shift Register(LFSR) for scrambling transmitted data; and a receive Linear FeedbackShift Register (LFSR) for descrambling transmitted data; each saidtransmit LFSR being initialized with a respective unique value per linkinstance during power-on of the multiple serial links, each saidtransmit LFSR starts running responsive to said respective initializedunique value per link instance, and continues running during life of thepower-on; each said respective initialized unique value per linkinstance being different from one another and substantially withoutadding of EMI radiation of each link; and each said transmit LFSRperforming a link training sequence to initialize each of the multipleserial links, said link training sequence including each said transmitLFSR conveying a respective current unique value per link instance to areceive LFSR for synchronizing said transmit LFSR and said receive LFSRto begin scrambling data; each said respective current unique value perlink instance being different from one another for each said transmitLFSR.
 6. The multiple-path local rack interconnect system as recited inclaim 5 wherein said unique value is based upon an interface number ofeach said transmit LFSR.
 7. A design structure embodied in a machinereadable medium used in a design process, the design structurecomprising: a circuit tangibly embodied in the machine readable mediumused in the design process, said circuit for implementing knownscrambling relationship among multiple serial links, said circuitcomprising: a respective link interface coupled to each of the multipleserial links, each said link interface including a transmit LinearFeedback Shift Register (LFSR) for scrambling transmitted data; and areceive Linear Feedback Shift Register (LFSR) with each of the multipleserial links for descrambling transmitted data; each said transmit LFSRbeing initialized with a respective unique value per link instanceduring power-on of the multiple serial links, each said transmit LFSRstarts running responsive to said respective initialized unique valueper link instance, and continues running during life of the power-on;each said respective initialized unique value per link instance beingdifferent from one another and substantially without adding of EMIradiation of each link; and each said transmit LFSR performing a linktraining sequence to initialize each of the multiple serial links, saidlink training sequence including each said transmit LFSR, conveying arespective current unique value per link instance to a receive LFSR, forsynchronizing said transmit LFSR and said receive LFSR to beginscrambling data; each said respective current unique value per linkinstance being different from one another for each said transmit LFSR,wherein the design structure, when read and used in the manufacture of asemiconductor chip produces a chip comprising said circuit.
 8. Thedesign structure of claim 7, wherein the design structure comprises anetlist, which describes said circuit.
 9. The design structure of claim7, wherein the design structure resides on storage medium as a dataformat used for the exchange of layout data of integrated circuits. 10.The design structure of claim 7, wherein the design structure includesat least one of test data files, characterization data, verificationdata, or design specifications.
 11. The design structure of claim 7,wherein said unique value is based upon an interface number of each saidtransmit LFSR.